A sound clone ATXMEGA128A4U-MH locked MCU program assessment is a technical document, not a claim. The ATXMEGA128A4U-MH exposes its signature and fuse bytes over PDI while keeping a locked application array closed. MH selects the 44-pad QFN body on the top-capacity part, where board-level decoupling dominates the rework notes.

Limits and options for clone ATXMEGA128A4U-MH locked MCU program

At the top of the A4U line the same 8/16-bit XMEGA RISC pipeline delivers 32 MIPS at 32 MHz, but the larger SRAM and the doubled boot section change how a USB application is structured. Thirty-two working registers sit directly on the ALU, most instructions complete in one cycle, and a programmable multilevel interrupt controller handles peripheral traffic. The device runs from 1.6 to 3.6 V, with the full 32 MHz ceiling only above 2.7 V and a 12 MHz limit at the lowest rail. Source code, a compiled binary and the contents of flash are three different levels of evidence on any integrated circuit.

Application, boot and EEPROM regions

This member carries 128 Kbytes of in-system self-programmable flash, an 8 Kbyte boot code section, 8 Kbytes of SRAM and 2 Kbytes of EEPROM. The 8 Kbyte boot section is the family’s largest, and its independent lock bits mean a bootloader image has to be archived separately from the application. Flash endurance exceeds 10,000 erase/write cycles, EEPROM 100,000, both with 20-year retention, and CRC-16 and CRC-32 generators are provided for integrity checks. The 32 MHz ceiling only applies above 2.7 V; a board running at 1.8 V must stay within the 12 MHz limit stated in the datasheet. A heximal export must label application pages, boot pages, EEPROM, fuse bytes and the calibration row; collapsing them into one binary file makes later source code reconstruction unreliable. The surrounding XMEGA and general AVR material is linked here: ATXMEGA16A4U-AU flash documentation.

Identification without a readout

Independent lock-bit groups cover the boot section and the application flash, and the calibration row is separately protected on this member. The AES/DES engine, the DMA controller and the event system are application features and provide no service route around the lock field. Chip erase is the operation that clears protection, and it removes the application and EEPROM contents in the process. Related device notes on this site cover the wider family: ATXMEGA32A4U-AU flash documentation.

Clock, USB and ADC references

USB 2.0 full-speed device operation at 12 Mbps with 32 endpoints and an on-chip transceiver regulator is standard, as are the four-channel DMA controller and the eight-channel event system that let peripherals communicate without CPU involvement. Five USARTs (one IrDA capable), two TWI ports with dual address match and two SPI ports cover serial traffic. A microcontroller with its lock bits set still yields a usable documentation package: marking, memory, code and data regions, and a signed archive comparison. For background on a neighbouring part, see ATXMEGA64A4U-MHR flash documentation.

Footprint comparison across the line

AU is the 44-lead TQFP, AUR its reel-packed form and MH the 44-pad QFN; all three expose 34 programmable I/O lines and the dedicated PDI pair, and all carry the same 128 Kbyte die. An 8 Kbyte boot section can hold a complete USB bootloader, so its lock group deserves a separate entry in any archive manifest. Power sequencing and the reset source are recorded before a programmer is attached, because a misread rail on a dense QFN board is expensive to repair. A trailing R is a packing code, not a change to the memory map or the lock behaviour. The AVR cross-reference is documented in Break chip atmega48pa firmware.

Documentation deliverables and terms

This is the largest A4U member, and its 8 Kbyte boot section is double that of the lower capacities while SRAM reaches 8 Kbytes. Every member keeps the same 44-pin or 49-ball footprint, USB device controller, PDI interface and analogue block, so a schematic alone cannot identify which die is fitted. Our written scope covers the package marking, ordering code, PDI signature, fuse bytes, clock source and supply rails, then a comparison with the owner’s release archive. Where the array is unlocked we return separate labelled images for application flash, the 8 Kbyte boot section and the EEPROM calibration data. Where lock bits are set we supply an identification and documentation package and state plainly that chip erase destroys the application. A comparable recovery note is Break chip atmega48pa heximal.

Owners considering clone ATXMEGA128A4U-MH locked MCU program should expect a technical deliverable first: a datasheet-based identification record, a labelled image where the lock bits permit one, and a clear written statement where they do not. We explain that a chip erase removes the firmware together with the protection, require written authorisation before any destructive step, and never price a service that depends on defeating the lock field. That boundary is what keeps a recovered program file usable as evidence years later.

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