On a small part, initialisation is short: set the stack pointer, configure a port, start a timer. On a large one there is more to establish before the application can run, and the order in which it is established describes the hardware the firmware expects to find.

The first hundred instructions are therefore the highest-value region of the image, and they are readable without any understanding of the application that follows.

The sequence, and what each step proves

The third row is the one that answers a question no schematic reading can settle quickly: whether the board has external memory. A build that programs the interface registers is a build that expects it, and the wait-state values describe how fast it is.

Why the order is informative

Runtimes initialise in dependency order. Nothing that uses the stack comes before the stack pointer is set. Nothing that reads a table comes before the address extension is configured. Nothing that depends on time comes before the clock.

So the order is a partial specification of the firmware’s dependencies. If the serial port is initialised before the clock is configured, either the serial port uses an independent clock or the sequence is wrong — and a wrong sequence in a shipping product is worth knowing about.

What the stack pointer says

The value written to the stack pointer is an address in data space. Its position tells you how the linker laid out the build: stack at the top of RAM growing down is conventional, and the exact value reveals how much RAM the design assumes.

On a part with more RAM than a small sibling, a stack pointer set well above the low addresses means the build uses the space, which means there are buffers, which means there is something to buffer. That inference alone often identifies the product’s category.

Port configuration as an interface description

The port direction registers describe the hardware as well as any schematic:

• Pins set as outputs with an initial low state are drivers waiting to be activated.
• Pins set as inputs with pull-ups enabled are switch or open-collector inputs.
• Pins left as inputs without pull-ups are either unused or driven externally.
• Pins toggled immediately after configuration are indicators or handshake lines.

Reading that list against the product’s function usually produces a complete description of the interface before any application code is examined.

The low-voltage grade

V extends the supply range downward, which affects one thing in this region: the clock configuration. A part configured to run at full speed from a low supply is at the edge of its specification, and the prescaler setting is where that trade is recorded.

A build that divides the clock on a low-voltage part is a build that acknowledged the constraint. A build that does not is worth a second look, because it may have been validated at a rail the product does not actually provide.

Reading order

1. Read fuses and lock byte before the array.
2. Read the array, verified.
3. Decode the reset vector; start reading at its target.
4. Read the first hundred instructions in full, annotating each group.
5. Use the annotated groups as the index for the rest of the analysis.

Step 5 is why this is worth doing first. Initialisation names the subsystems, and the subsystems are the chapters of everything that follows.

Related notes

• ATmega128V and the boundary register — the extension mechanism in detail.
• ATmega128PV and long-read drift — reading this much flash reliably.
• ATmega640 and external memory — the interface these registers configure.

FAQ

Is initialisation always in the same order? Broadly, because dependencies force it. Vendor start-up code establishes the pattern.

What if the stack pointer is set to the very top of RAM? That is conventional and says little; a value below the top suggests reserved space.

Can external memory be detected without the registers? Only by inspecting the board. The firmware tells you what it expects.

Does the clock setting have to come first? Before anything time-dependent, yes.

Conclusion

The reset path is a specification written by the firmware about its own hardware. Stack, address extension, memory interface, clock, ports, peripherals — six groups that name the chapters of the analysis and answer questions a schematic cannot. Reading them first is the highest return per instruction in the entire image.

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