Archive for the ‘Attack MCU’ Category

PostHeaderIcon Break IC ATTINY261 Code

Break IC ATTINY261 Code

Break IC ATTINY261 Code

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High Performance, Low Power AVR® 8-Bit Microcontroller

Advanced RISC Architecture

– 123 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation when Break IC

 

Non-volatile Program and Data Memories

– 2/4/8K Byte of In-System Programmable Program Memory Flash

 

(ATtiny261/461/861)

Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261)

Endurance: 100,000 Write/Erase Cycles

– 128/256/512 Bytes Internal SRAM (ATtiny261/461/861)

– Programming Lock for Self-Programming Flash Program and EEPROM Data Security

Peripheral Features

– 8/16-bit Timer/Counter with Prescaler and Two PWM Channels

– 8/10-bit High Speed Timer/Counter with Separate Prescaler after Break IC

3 High Frequency PWM Outputs with Separate Output Compare Registers

Programmable Dead Time Generator

– Universal Serial Interface with Start Condition Detector

– 10-bit ADC

11 Single Ended Channels

16 Differential ADC Channel Pairs

15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)

– Programmable Watchdog Timer with Separate On-chip Oscillator if Break IC

– On-chip Analog Comparator

Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

I/O and Packages

– 16 Programmable I/O Lines after Break IC

– 20-pin PDIP, 20-pin SOIC and 32-pad MLF

Operating Voltage:

– 1.8 – 5.5V for ATtiny261

– 2.7 – 5.5V for ATtiny261

Speed Grade:

– ATtiny261V/461V/861V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V when Break IC

– ATtiny261/461/861: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V

– Active Mode: 1 MHz, 1.8V: 380ìA

– Power-down Mode: 0.1ìA at 1.8V

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized before Break IC.

The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

PostHeaderIcon Break IC PIC16C771 Firmware

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The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section. For example, CLRF STATUS will clear the upper-three when Break IC;

The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended after Break IC.

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the ”Instruction Set Summary. when Break IC

The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register occur through the PCLATH register after Break IC.

PIC16C717/770/771 devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program

memory page. When doing aCALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. A return instruction pops a PC address off the stack onto the PC register. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack) before Break IC.

The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Mid-range devices have an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of  RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed if Break IC.

After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing before Break IC.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1 Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin if Break IC.

Additional information on I/O ports may be found in the PICmicro™  Mid-Range  Reference  Manual, (DS33023).

PORTA is a 8-bit wide bi-directional port. The corre-analog mode of the corresponding pins. sponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch after Break IC.

Pins RA<3:0> are multiplexed with analog functions, such as analog inputs to the A/D converter, analog VREF inputs, and the on-board bandgap reference outputs. When the analog peripherals are using any of Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output before Break IC.

Pin RA5 is multiplexed with the device reset (MCLR) and programming input (VPP) functions. The RA5/ MCLR/VPP input only pin has a Schmitt Trigger input buffer. All other RA port pins have Schmitt Trigger input buffers and full CMOS output buffers.

Pins RA6 and RA7 are multiplexed with the oscillator input and output functions when Break IC.

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

PostHeaderIcon Reverse Engineering Microcontroller PIC16F882 Heximal

Reverse engineering Microcontroller PIC16F882 Heximal

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High-Performance RISC CPU:

· Only 35 Instructions to Learn:

– All single-cycle instructions except branches

· Operating Speed:

– DC – 20 MHz oscillator/clock input

– DC – 200 ns instruction cycle when Reverse engineering Microcontroller

· Interrupt Capability

· 8-Level Deep Hardware Stack

· Direct, Indirect and Relative Addressing modes

Special Microcontroller Features:

· Precision Internal Oscillator:

– Factory calibrated to ±1%

– Software selectable frequency range of 8 MHz to 31 kHz after Reverse engineering Microcontroller

– Software tunable

– Two-Speed Start-up mode

– Crystal fail detect for critical applications

– Clock mode switching during operation for power savings

· Power-Saving Sleep mode

· Wide Operating Voltage Range (2.0V-5.5V)

· Industrial and Extended Temperature Range

· Power-on Reset (POR)

· Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) if Reverse engineering Microcontroller

· Brown-out Reset (BOR) with Software Control Option

· Enhanced Low-Current Watchdog Timer (WDT) with On-Chip Oscillator (software selectable nominal 268 seconds with full prescaler) with software enable

· Multiplexed Master Clear with Pull-up/Input Pin

· Programmable Code Protection

· High Endurance Flash/EEPROM Cell:

– 100,000 write Flash endurance

– 1,000,000 write EEPROM endurance after Reverse engineering Microcontroller

– Flash/Data EEPROM retention: > 40 years

· Program Memory Read/Write during run time

· In-Circuit Debugger (on board)

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PostHeaderIcon Recover Chip PIC16HV785 Hex

Recover Chip PIC16HV785 Hex

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PROGRAM MEMORY ORGANIZATION

The PIC16F785/HV785 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC16F785/HV785 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h recover chip.

DATA MEMORY ORGANIZATION

The data memory is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static RAM. The last sixteen register locations in Bank 1 (F0h-FFh), Bank 2 (170h-17Fh), and Bank 3 (1F0h-1FFh) point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read after recover chip.

PROGRAM MEMORY MAP AND STACK FOR THE PIC16F785/HV785 if recover chip

Seven address bits are required to access any location in a data memory bank. Two additional bits are required to access the four banks. When data memory is accessed directly, the seven Least Significant address bits are contained within the opcode and the two Most Significant bits are contained in the STATUS register for the purpose of recover chip.

RP0 and RP1 bits of the STATUS register are the two Most Significant data memory address bits and are also known as the bank select bits. Table 2-1 lists how to access the four banks of registers when RECOVER MCU.

PostHeaderIcon Attack MCU PIC16F636 Binary

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Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer after Attack MCU.

Timer1 Oscillator

A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 32 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 9-2 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the system clock is derived from the internal oscillator.

Asynchronous Counter Mode if Attack MCU.

As with the system LP oscillator, the user must provide a software time delay to ensure proper oscillator start-up.

TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 read as ‘0’ and TRISA5 and TRISA4 bits read as ‘1’

The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the system clock is derived from the internal oscillator when Attack MCU.

Asynchronous Counter Mode.

Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer oscillator is enabled. RA5 and RA4 read as ‘0’ and TRISA5 and TRISA4 bits read as ‘1’ in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads after Attack MCU.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register.

Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode for the purpose of Attack MCU.

PostHeaderIcon Attack MCU PIC16F676 Code

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This document contains device specific information for the PIC16F630/676. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this Data Sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules when Attack MCU code.

The PIC16F630 and PIC16F676 devices are covered by this Data Sheet. They are identical, except the PIC16F676 has a 10-bit A/D converter. They come in 14-pin PDIP, SOIC and TSSOP packages. Figure 1-1 shows a block diagram of the PIC16F630/676 devices. Table 1-1 shows the pinout description after Attack MCU code.

PROGRAM MEMORY ORGANIZATION

The PIC16F630/676 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h – 03FFh) for the PIC16F630/676 devices is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first 1K x 14 space.

The RESET vector is at 0000h and the interrupt vector is at 0004h for the purpose of Attack MCU code.

DATA MEMORY ORGANIZATION

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose registers and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit after Attack MCU code.

SPECIAL FUNCTIONS REGISTERS

The Special Function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature if Attack MCU code.

PostHeaderIcon Attack MCU PIC16F630 Firmware

Attack MCU PIC16F630 Firmware

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High Performance RISC CPU:

· Only 35 instructions to learn

– All single cycle instructions except branches when attack MCU

· Operating speed:

– DC – 20 MHz oscillator/clock input

– DC – 200 ns instruction cycle

· Interrupt capability

· 8-level deep hardware stack

· Direct, Indirect, and Relative Addressing modes

 

Special Microcontroller Features:

· Internal and external oscillator options

– Precision Internal 4 MHz oscillator factory calibrated to ±1% after attack MCU

– External Oscillator support for crystals and resonators

– 5 µs wake-up from SLEEP, 3.0V, typical

· Power saving SLEEP mode

· Wide operating voltage range – 2.0V to 5.5V

· Industrial and Extended temperature range

· Low power Power-on Reset (POR)

· Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

· Brown-out Detect (BOD)

· Watchdog Timer (WDT) with independent oscillator for reliable operation if attack MCU

· Multiplexed MCLR/Input-pin

· Interrupt-on-pin change

· Individual programmable weak pull-ups

· Programmable code protection

· High Endurance FLASH/EEPROM Cell

– 100,000 write FLASH endurance

– 1,000,000 write EEPROM endurance

– FLASH/Data EEPROM Retention: > 40 years for the purpose of attack MCU

 

Low Power Features:

· Standby Current:

– 1 nA @ 2.0V, typical

· Operating Current:

– 8.5 µA @ 32 kHz, 2.0V, typical

– 100 µA @ 1 MHz, 2.0V, typical

· Watchdog Timer Current

– 300 nA @ 2.0V, typical

· Timer1 oscillator current:

– 4 µA @ 32 kHz, 2.0V, typical Peripheral Features after attack MCU:

· 12 I/O pins with individual direction control

· High current sink/source for direct LED drive

· Analog comparator module with:

One analog comparator

– Programmable on-chip comparator voltage reference (CVREF) module

– Programmable input multiplexing from device inputs

– Comparator output is externally accessible

· Analog-to-Digital Converter module (PIC16F676):

– 10-bit resolution

– Programmable 8-channel input

– Voltage reference input

· Timer0: 8-bit timer/counter with 8-bit programmable prescaler

· Enhanced Timer1:

– 16-bit timer/counter with prescaler

– External Gate Input mode

– Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTOSC mode selected

· In-Circuit Serial ProgrammingTM (ICSPTM) via two pins

PostHeaderIcon Attack MCU PIC12F675 Binary

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This document contains device specific information for the PIC12F629/675. Additional information may be found in the PIC® Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this Data  Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules when attack MCU.

The PIC12F629 and PIC12F675 devices are covered by this Data Sheet. They are identical, except the PIC12F675 has a 10-bit A/D converter. They come in 8-pin PDIP, SOIC, MLF-S and DFN packages. Figure 1-1 shows a block diagram of the PIC12F675 devices. Table 1-1 shows the pinout description after attack MCU.

The PIC12F629/675 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC12F629/675 devices is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space.

The Reset vector is at 0000h and the interrupt vector is at 0004h if attack MCU.

The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose locations of each bank. Register locations 20h-5Fh are General Purpose Registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit for the purpose of attack MCU.

Registers and the Special Function Registers. The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-5Fh are General Purpose Registers, implemented as static RAM and are mapped across both banks. All other RAM is unimplemented and returns ‘0’ when read. RP0 (STATUS<5>) is the bank select bit when attack MCU.

PostHeaderIcon Attack PIC MCU 16F506 Code

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High-Performance RISC CPU:

· Only 33 single-word instructions to learn

· All single-cycle instructions except for program branches, which are two-cycle

· 12-bit wide instructions

· 2-level deep hardware stack

· Direct, Indirect and Relative Addressing modes for data and instructions

· 8-bit wide data path

· 10 Special Function Hardware registers (PIC12F510)

· 13 Special Function Hardware registers (PIC16F506)

· Operating speed:

– DC – 8 MHz Crystal Oscillator (PIC12F510)

– DC – 500 ns instruction cycle (PIC12F510)

– DC – 20 MHz Crystal Oscillator (PIC16F506)

– DC – 200 ns instruction cycle (PIC16F506)

Special Microcontroller Features:

· 4 or 8 MHz selectable precision internal oscillator:

– Factory calibrated to ±1% when attack PIC MCU

· In-Circuit Serial Programming™ (ICSP™)

· In-Circuit Debugging (ICD) support

· Power-on Reset (POR)

· Device Reset Timer (DRT):

– Short DRT (1.125 ms, typical) for INTOSC, EXTRC and EC

– DRT (18 ms, typical) for HS, XT and LP

· Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation

· Programmable code protection

· Multiplexed MCLR input pin if attack PIC MCU

· Selectable internal weak pull-ups on I/O pins

· Power-Saving Sleep mode

· Wake-up from Sleep on pin change

· Wake-up from Sleep on comparator change

Selectable oscillator options:

– INTOSC: 4/8 MHz precision Internal oscillator

– EXTRC: External low-cost RC oscillator

– XT: Standard crystal/resonator

– LP: Power-saving, low-frequency crystal

– HS: High-speed crystal/resonator (PIC16F506 only)

– EC: High-speed external clock input (PIC16F506 only) after Attack PIC MCU 16F506 Code

· Analog-to-Digital (A/D) Converter:

– 8-bit resolution

– 4-input channels (1 channel is dedicated to conversion of the internal 0.6V absolute voltage reference)

· High current sink/source for direct LED drive

· 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler

 

Low-Power Features/CMOS Technology:

· Operating Current:

– < 170 ìA @ 2V, 4 MHz

· Standby Current:

– 100 nA @ 2V, typical

· Low-power, high-speed Flash technology:

– 100,000 cycle Flash endurance for the purpose of recover MCU

– > 40-year retention

· Fully static design

· Wide operating voltage range: 2.0V to 5.5V

· Wide temperature range:

– Industrial: -40°C to +85°C

– Extended: -40°C to +125°C e:AR-SA’>programmable prescaler

PostHeaderIcon Attack MCU PIC16C712 Binary

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Microcontroller Core Features:

· High-performance RISC CPU

· Only 35 single word instructions to learn

· All single cycle instructions except for program branches which are two cycle when Attack MCU PIC16C712 Binary

· Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle

· Interrupt capability (up to 7 internal/external interrupt sources)

· Eight level deep hardware stack

· Direct, indirect and relative addressing modes

· Power-on Reset (POR)

· Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

· Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

· Brown-out detection circuitry for Brown-out Reset (BOR)

· Programmable code-protection

· Power saving SLEEP mode

· Selectable oscillator options

· Low-power, high-speed CMOS EPROM technology

· Fully static design

· In-Circuit Serial Programming™ (ICSP) after Attack MCU PIC16C712 Binary

· Wide operating voltage range: 2.5V to 5.5V

· High Sink/Source Current 25/25 mA

· Commercial, Industrial and Extended temperature ranges

· Low-power consumption:

– < 2 mA @ 5V, 4 MHz

– 22.5 µA typical @ 3V, 32 kHz

– < 1 µA typical standby current

Peripheral Features:

· Timer0: 8-bit timer/counter with 8-bit prescaler

· Timer1: 16-bit timer/counter with prescaler can be incremented during sleep via external crystal/clock

· Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

· Capture, Compare, PWM module

· Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit

· 8-bit multi-channel Analog-to-Digital converter

This document contains device-specific information. Additional information may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website when Attack MCU. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules before Attack MCU PIC16C712 Binary.

There are two devices (PIC16C712, PIC16C716) covered by this datasheet. Figure 1-1 is the block diagram for both devices. The pinouts are listed in Table 1-1.