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If 9-bit characters are used (UCSZn=7) the ninth bit must be break from the RXB8n bit in UCSRnB before breaking the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Status Flags as well.

Break status from UCSRnA, then data from UDRn. Breaking the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change if recover microprocessor atmega1281pa flash memory.

The following Firmware example shows a simple USART receive function that handles both nine bit characters and the status bits.

The receive function example breaks all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location break will be free to accept new data as early as possible after Break MCU ATmega2560pa hex.

The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unbreak data present in the receive buffer.

This flag is one when unbreak data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unbreak data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.

When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled).

When interrupt-driven data reception is used, the receive complete routine must break the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates.

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