Archive for June, 2014

PostHeaderIcon Attack IC TMS320BC57 Flash

Attack IC TMS320BC57 Flash

Attack IC TMS320BC57 Flash

We can Attack IC TMS320BC57 Flash, please view below IC TMS320BC57 features for your reference:

Powerful 16-Bit TMS320C5x CPU 20-, 25-, 35-, and 50-ns Single-Cycle

Instruction Execution Time for 5-V

Operation

25-, 40-, and 50-ns Single-Cycle Instruction

Execution Time for 3-V Operation

Single-Cycle 16 × 16-Bit Multiply/Add 224K × 16-Bit Maximum Addressable

External Memory Space (64K Program, 64K

Data, 64K I/O, and 32K Global)

2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access

On-Chip Program ROM

1K, 3K, 6K, 9K × 16-Bit Single-Access

On-Chip Program / Data RAM (SARAM)

1K Dual-Access On-Chip Program / Data

RAM (DARAM)

Full-Duplex Synchronous Serial Port for Coder/Decoder Interface to crack MCU

Time-Division-Multiplexed (TDM) Serial Port

Hardware or Software Wait-State

Generation Capability

On-Chip Timer for Control Operations

Repeat Instructions for Efficient Use of

Program Space

Buffered Serial Port

Host Port Interface

 

Multiple Phase-Locked Loop (PLL)

Clocking Options (×1, ×2, ×3, ×4, ×5, ×9

Depending on Device)

Block Moves for Data/Program

Management

On-Chip Scan-Based Emulation Logic

Boundary Scan

Five Packaging Options

– 100-Pin Quad Flat Package (PJ Suffix)

– 100-Pin Thin Quad Flat Package (PZ Suffix)

– 128-Pin Thin Quad Flat Package (PBK Suffix)

– 132-Pin Quad Flat Package (PQ Suffix)

– 144-Pin Thin Quad Flat Package (PGE Suffix)

Low Power Dissipation and Power-Down

Modes:

– 47 mA (2.35 mA / MIP) at 5 V, 40-MHz Clock (Average)

– 23 mA (1.15 mA / MIP) at 3 V, 40-MHz

 

Description

The TMS320C5x generation of the Texas Instruments (TI™ ) TMS320 digital signal processors (DSPs) is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the ’C5x‡ devices. They execute up to 50 million instructions per second (MIPS).

The ’C5x devices offer these advantages: Enhanced TMS320 architectural design for increased performance and versatility Modular architectural design for fast development of spin-off devices Advanced integrated-circuit processing technology for increased performance Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.) Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation New static-design techniques for minimizing power consumption and maximizing radiation tolerance Clock (Average).

– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)

– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)

– 5 µA at 5 V, Clocks Off (IDLE2 Mode)

 

High-Performance Static CMOS Technology

IEEE Standard 1149.1† Test-Access Port (JTAG)

PostHeaderIcon Break Chip PIC12CR509A Flash

Break Chip PIC12CR509A Flash

Break Chip PIC12CR509A Flash

 

The PIC12CE518 and PIC12CE519 each have 16 bytes of EEPROM data memory which is a necessary part for Break Chip PIC12CR509A Flash. The EEPROM memory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol.

These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 that are connected to the I/O pins, SDA and SCL are only connected to the internal EEPROM peripheral. For most applications, all that is required is calls to the following functions:

The code for these functions is available on our website www.microchip.com. The code will be accessed by either including the source code FL51XINC.ASM or by linking FLASH5IX.ASM. It is very important to check the return codes when using these calls, and retry the operation if unsuccessful.

Unsuccessful return codes occur when the EE data memory is busy with the previous write, which can take up to 4 mS. SDA is a bi-directional pin used to transfer addresses and data into and data out of the device before Break chip.

For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. The EEPROM interface is a 2-wire bus protocol consisting of data (SDA) and a clock (SCL).

Although these lines are mapped into the GPIO register, they are not accessible as external pins; only to the i internal EEPROM peripheral. SDA and SCL operation is also slightly different than GPO-GP5 as listed below. Namely, to avoid code overhead in modifying the TRIS register, both SDA and SCL are always outputs.

To read data from the EEPROM peripheral requires outputting a ‘1’ on SDA placing it in high-Z state when Reading MCU, where only the internal 100K pull-up is active on the SDA line. SDA:

Built-in 100K (typical) pull-up to VDD Open-drain (pull-down only)

Always an output

Outputs a ‘1’ on reset

SCL:

Full CMOS output

Always an output

Outputs a ‘1’ on reset

The following example requires:

· Code Space: 77 words

· RAM Space: 5 bytes (4 are overlayable)

· Stack Levels:1 (The call to the function itself. The functions do not call any lower level functions.)

· Timing:

– WRITE_BYTE takes 328 cycles

– READ_CURRENT takes 212 cycles

– READ_RANDOM takes 416 cycles.

· IO Pins: 0 (No external IO pins are used)

This code must reside in the lower half of a page. The code achieves it’s small size without additional calls through the use of a sequencing table. The table is a list of procedures that must be called in order. The table uses an ADDWF PCL,F instruction, effectively a computed goto, to sequence to the next procedure if Break chip.

However the ADDWF PCL,F instruction yields an 8 bit address, forcing the code to reside in the first 256 addresses of a page.

PostHeaderIcon Break Microcontroller PIC16F886 Software

Break Microcontroller PIC16F886 Software

Break Microcontroller PIC16F886 Software

We can Break Microcontroller PIC16F886 Software, please view the Microcontroller PIC16F886 features for your reference:

The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared.

Figure 2-7 shows the two situations for the loading of the PC. The upper example in Figure 2-7 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-7 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH to Copy microcontroller.

The PIC16F882/883/884/886/887 devices have an 8-level x 13-bit wide hardware stack (see Figures 2-2 and 2-3). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable when Extract MCU. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

PostHeaderIcon Break IC TMS320F28044 Heximal

Break IC TMS320F28044 Heximal

Break IC TMS320F28044 Heximal

We can Break IC TMS320F28044 Heximal, please view below IC TMS320F28044 features for your reference:

F28044 Digital Signal Processor

Features

· High-Performance 100-MHz (10-ns Cycle Time) Processor

· TMS320C28x™ 32-Bit CPU

– Single-cycle 16 × 16 and 32 × 32

Multiply-accumulate (MAC) Operations

– Dual 16 × 16 MAC

– Fast Interrupt Response

– Unified Memory Programming Model

· On-Chip Memory

– 64K × 16 Flash

– 10K × 16 SARAM

– 1K × 16 OTP

– 4K × 16 Boot ROM

– Code Security Module Protects Against

Unauthorized Memory Access

· Clocking

– Dynamic PLL Ratio Changes Supported

– On-Chip Oscillator

– Clock-Fail-Detect Mode

· Interrupts

– Support for up to Three External Core Interrupts

– Peripheral Interrupt Expansion (PIE) Block

That Supports All Peripheral Interrupts

· High-speed, 12-Bit ADC

– 80 ns (12.5 MSPS) Conversion Rate

– 16 Channels

– Two Sample-and-Hold

– Single/Simultaneous Conversions

– Internal or External Reference

· High-Resolution PWM

– 16 Outputs with 150 ps Resolution

– 14.8 Bits at 200-kHz Switching

– 13.4 Bits at 500-kHz Switching

– 12.4 Bits at 1-MHz Switching

· Communications Port Peripherals to extract IC code

– Serial Peripheral Interface (SPI) Module

– Serial Communications Interface (SCI)

– Inter-Integrated Circuit (I2C) Bus

· Timers

– Three 32-bit CPU Timers

– Up to 16 16-bit Timers

– Watchdog Timer Module

· Up to 35 General-Purpose Input/Output (GPIO) Pins With Input Filtering

· On-chip JTAG Emulation With Real-time Debug via Hardware

· JTAG Boundary Scan Support

· Low-power IDLE, STANDBY, and HALT Modes

· Development Tools

– F28044 eZdsp Starter Kit

– Code Composer Studio™ IDE With Flash Programming Plug-in

– C28x-optimized ANSI C/C++

Compiler/Assembler/Linker

– DSP/BIOS™ Real-time Operating System

– USB-based JTAG Emulators (1)

· Available Software

– C2000™ Digital Power Supply Software Library

– C28x™ IQ Math Library

– C28x Header Files With Example Programs for all Peripherals

– C28x DSP Library

– C28x Digital Motor Control Software Library

· Package Options

– 100-pin Thin Quad Flatpack (PZ)

– 100-pin MicroStar BGA™ (GGM, ZGM)

– RoHS-compliant, Green Packaging

· Temperature Range:

A: –40°C to 85°C (PZ, GGM, ZGM)

PostHeaderIcon Copy Microcontroller PIC16F627A Software

Copy Microcontroller PIC16F627A Software

Copy Microcontroller PIC16F627A Software

We can Copy Microcontroller PIC16F627A Software, please view below Microcontroller PIC16F627A/628A features for your reference:

High-Performance RISC CPU:

Low-Power Features:

Operating speeds from DC – 20 MHz

Interrupt capability

8-level deep hardware stack

Direct, Indirect and Relative Addressing modes

35 single-word instructions:

– All instructions single cycle except branches

· Standby Current:

– 100 nA @ 2.0V, typical

· Operating Current:

– 12 ìA @ 32 kHz, 2.0V, typical

– 120 ìA @ 1 MHz, 2.0V, typical

· Watchdog Timer Current

– 1 ìA @ 2.0V, typical

Special Microcontroller Features:

· Internal and external oscillator options:

– Precision internal 4 MHz oscillator factory calibrated to ±1%

– Low-power internal 48 kHz oscillator

– External Oscillator support for crystals and resonators

· Power-saving Sleep mode to faciliate MCU Cracking

· Programmable weak pull-ups on PORTB

· Multiplexed Master Clear/Input-pin

· Watchdog Timer with independent oscillator for reliable operation

· Low-voltage programming

· In-Circuit Serial Programming™ (via two pins)

· Programmable code protection

· Brown-out Reset

· Power-on Reset

· Power-up Timer and Oscillator Start-up Timer

· Wide operating voltage range (2.0-5.5V)

· Industrial and extended temperature range

· High-Endurance Flash/EEPROM cell:

– 100,000 write Flash endurance

– 1,000,000 write EEPROM endurance

– 40 year data retention

· Timer1 Oscillator Current:

– 1.2 ìA @ 32 kHz, 2.0V, typical

· Dual-speed Internal Oscillator:

– Run-time selectable between 4 MHz and 48 kHz

– 4 ìs wake-up from Sleep, 3.0V, typical

 

Peripheral Features:

· 16 I/O pins with individual direction control

· High current sink/source for direct LED drive

· Analog comparator module with:

– Two analog comparators

– Programmable on-chip voltage reference (VREF) module

– Comparator outputs are externally accessible

· Timer0: 8-bit timer/counter with 8-bit programmable prescaler

· Timer1: 16-bit timer/counter with external crystal/ clock capability

· Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

· Capture, Compare, PWM module:

– 16-bit Capture/Compare

– 10-bit PWM

· Addressable Universal Synchronous/Asynchronous Receiver/Transmitter USART/SCI

PostHeaderIcon Copy MCU PIC18F2480 Program

Copy MCU PIC18F2480 Program

Copy MCU PIC18F2480 Program

We can Copy MCU PIC18F2480 Program, below MCU PIC18F2480 features for your reference:

Power-Managed Modes:

Peripheral Highlights:

Run: CPU on, Peripherals on

Idle: CPU off, Peripherals on

Sleep: CPU off, Peripherals off

Idle mode Currents Down to 6.1 ìA Typical

Sleep mode Current Down to 0.2 ìA Typical

Timer1 Oscillator: 1 ìA, 32 kHz, 2V

Watchdog Timer: 1.7 ìA

Two-Speed Oscillator Start-up

High-Current Sink/Source 25 mA/25 mA

Three External Interrupts

One Capture/Compare/PWM (CCP) module

Enhanced Capture/Compare/PWM (ECCP) module

(40/44-pin devices only):

– One, two or four PWM outputs

– Selectable polarity

– Programmable dead time

Flexible Oscillator Structure:

· Four Crystal modes, up to 40 MHz

· 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators)

· Two External RC modes, up to 4 MHz

· Two External Clock modes, up to 40 MHz

· Internal Oscillator Block:

– Fast wake from Sleep and Idle, 1 ìs typical

– Provides a complete range of clock speeds, from 31 kHz to 32 MHz when used with PLL

– User-tunable to compensate for frequency drift

· Secondary Oscillator using Timer1 @ 32 kHz

· Fail-Safe Clock Monitor

– Auto-shutdown and auto-restart

Master Synchronous Serial Port (MSSP) module

Supporting 3-Wire SPI (all 4 modes) and I2C™

Master and Slave modes

Enhanced Addressable USART module

– Supports RS-485, RS-232 and LIN/J2602

– RS-232 operation using internal oscillator block

– Auto-wake-up on Start bit

– Auto-Baud Detect

10-Bit, up to 11-Channel Analog-to-Digital

Converter (A/D) module, up to 100 ksps

– Auto-acquisition capability

– Conversion available during Sleep

Dual Analog Comparators with Input Multiplexing

– Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features:

· C Compiler Optimized Architecture with Optional Extended Instruction Set to Crack MCU

· 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical

· 1,000,000 Erase/Write Cycle Data EEPROM Memory Typical

· Flash/Data EEPROM Retention: > 40 Years

· Self-Programmable under Software Control

· Priority Levels for Interrupts

· 8 x 8 Single-Cycle Hardware Multiplier

· Extended Watchdog Timer (WDT):

– Programmable period from 41 ms to 131s

· Single-Supply 5V In-Circuit Serial Programming™ (ICSP™) via Two Pins

· In-Circuit Debug (ICD) via Two Pins

· Wide Operating Voltage Range: 2.0V to 5.5V if Copy MCU

 

ECAN Technology Module Features:

· Message Bit Rates up to 1 Mbps

· Conforms to CAN 2.0B Active Specification

· Fully Backward Compatible with PIC18XXX8 CAN modules

· Three Modes of Operation:

– Legacy, Enhanced Legacy, FIFO

· Three Dedicated Transmit Buffers with Prioritization

· Two Dedicated Receive Buffers

· Six Programmable Receive/Transmit Buffers

· Three Full 29-Bit Acceptance Masks

· 16 Full 29-Bit Acceptance Filters w/Dynamic Association

· DeviceNet™ Data Byte Filter Support

· Automatic Remote Frame Handling

· Advanced Error Management Features

 

PostHeaderIcon Copy IC PIC16LF877 Program

Copy IC PIC16LF877 Program

Copy IC PIC16LF877 Program

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Devices Included in this Data Sheet:

Analog Features:

· PIC16F873A

· PIC16F874A

· PIC16F876A

· PIC16F877A

· 10-bit, up to 8-channel Analog-to-Digital Converter (A/D)

· Brown-out Reset (BOR)

 

High-Performance RISC CPU:

· Only 35 single-word instructions to learn when Clone IC

· All single-cycle instructions except for program branches, which are two-cycle

· Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle

· Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory

· Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX microcontrollers

Peripheral Features:

· Timer0: 8-bit timer/counter with 8-bit prescaler

· Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via external crystal/clock

· Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

· Two Capture, Compare, PWM modules

– Capture is 16-bit, max. resolution is 12.5 ns

– Compare is 16-bit, max. resolution is 200 ns

– PWM max. resolution is 10-bit

· Synchronous Serial Port (SSP) with SPI™ (Master mode) and I2C™ (Master/Slave)

· Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection

· Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and CS controls (40/44-pin only)

· Brown-out detection circuitry for Brown-out Reset (BOR)

· Analog Comparator module with:

– Two analog comparators

– Programmable on-chip voltage reference (VREF) module

– Programmable input multiplexing from device inputs and internal voltage reference

– Comparator outputs are externally accessible

Special Microcontroller Features:

· 100,000 erase/write cycle Enhanced Flash program memory typical

· 1,000,000 erase/write cycle Data EEPROM memory typical

· Data EEPROM Retention > 40 years

· Self-reprogrammable under software control

· In-Circuit Serial Programming™ (ICSP™) via two pins

· Single-supply 5V In-Circuit Serial Programming

· Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

· Programmable code protection

· Power saving Sleep mode

· Selectable oscillator options

· In-Circuit Debug (ICD) via two pins CMOS Technology:

· Low-power, high-speed Flash/EEPROM technology

· Fully static design when Copy IC

· Wide operating voltage range (2.0V to 5.5V)

· Commercial and Industrial temperature ranges

· Low-power consumption

 

PostHeaderIcon Attack Chip ST62T00CB6 Firmware

Attack Chip ST62T00CB6 Firmware

Attack Chip ST62T00CB6 Firmware

We can Attack Chip ST62T00CB6 Firmware and extract its source code out of eeprom, please view below Chip ST62T00CB6 features for your reference:

Memories

– 1K or 2K bytes Program memory (OTP, EPROM, FASTROM or ROM) with read-out protection

– 64 bytes RAM

Clock, Reset and Supply Management

– Enhanced reset system

PDIP16

– Low voltage detector (LVD) for safe Reset and Crack MCU

– Clock sources: crystal/ceramic resonator or RC network, external clock, backup oscillator (LFAO)

– Oscillator safeguard (OSG)

SO16

– 2 Power saving modes: Wait and Stop

 

Interrupt Management

– 4 interrupt vectors plus NMI and RESET

– 9 external interrupt lines (on 2 vectors)

 

SSOP16

9 I/O Ports

– 9 multifunctional bidirectional I/O lines

– 4 alternate function lines

– 3 high sink outputs (20mA)

 

2 Timers

– Configurable watchdog timer

 

CDIP16W

– 8-bit timer/counter with a 7-bit prescaler

Analog Peripheral

(See Section 11.5 for Ordering Information)

– 8-bit ADC with 4 input channels (except on ST6203C) Instruction Set

Development Tools

– Full hardware/software development package

– 8-bit data manipulation

– 40 basic instructions

– 9 addressing modes

– Bit manipulation

PostHeaderIcon Attack Microcontroller MC68HC705P6ACDW Binary

Attack Microcontroller MC68HC705P6ACDW Binary

Attack Microcontroller MC68HC705P6ACDW Binary

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Features of the MC68HC705P6A include:

· Low cost

· M68HC05 core

· 28-pin SOIC, PDIP, or windowed DIP package

· 4672 bytes of user EPROM (including 48 bytes of page zero EPROM and 16 bytes of user vectors)

·  239 bytes of bootloader ROM

· 176 bytes of on-chip RAM

· 4-channel 8-bit A/D converter

· SIOP serial communications port

· 16-bit timer with output compare and input capture

· 20 bidirectional I/O lines and 1 input-only line

· PC0 and PC1 high-current outputs

· Single-chip, bootloader, and test modes

· Power-saving stop, halt, and wait modes

· Static EPROM mask option register (MOR) selectable options:

– COP watchdog timer enable or disable

– Edge-sensitive or edge- and level-sensitive external interrupt

– SIOP most significant bit (MSB) or least significant bit (LSB) first

– SIOP clock rates: OSC divided by 8, 16, 32, or 64

– Stop instruction mode, STOP or HALT

– EPROM security external lockout

– Programmable keyscan (pullups/interrupts) on PA0–PA7

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PostHeaderIcon Attack MCU TMX320F28027PTA Archive

Attack MCU TMX320F28027PTA Archive

Attack MCU TMX320F28027PTA Archive

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Highlights

– High-Efficiency 32-Bit CPU ( TMS320C28x™)

– 60-MHz, 50-MHz, and 40-MHz Devices

– Single 3.3-V Supply

– Integrated Power-on and Brown-out Resets

– Two Internal Zero-pin Oscillators

– Up to 22 Multiplexed GPIO Pins

– Three 32-Bit CPU Timers

– On-Chip Flash, SARAM, OTP Memory

– Code-security Module

– Serial Port Peripherals (SCI/SPI/I2C)

– Enhanced Control Peripherals

 

· Low Device and System Cost:

– Single 3.3-V Supply

– No Power Sequencing Requirement

– Integrated Power-on and Brown-out Resets

– Small Packaging, as Low as 38-Pin Available

– Low Power

– No Analog Support Pins

· Clocking:

– Two Internal Zero-pin Oscillators

– On-Chip Crystal Oscillator/External Clock Input

– Dynamic PLL Ratio Changes Supported

 

Enhanced Pulse Width Modulator (ePWM) And High-Resolution PWM (HRPWM)

 

– Watchdog Timer Module

– Missing Clock Detection Circuitry

· Enhanced Capture (eCAP)

· Analog-to-Digital Converter (ADC)

· On-Chip Temperature Sensor

· Comparator

– 38-Pin and 48-Pin Packages

· High-Efficiency 32-Bit CPU ( TMS320C28x™)

– 60 MHz (16.67-ns Cycle Time)

– 50 MHz (20-ns Cycle Time)

– 40 MHz (25-ns Cycle Time)

– 16 x 16 and 32 x 32 MAC Operations

– 16 x 16 Dual MAC

– Harvard Bus Architecture

– Atomic Operations

– Fast Interrupt Response and Processing

– Unified Memory Programming Model

– Code-Efficient (in C/C++ and Assembly)

· Endianness: Little Endian

 

· Up to 22 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

· Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts to Unlock Microcontroller

· Three 32-Bit CPU Timers

· Independent 16-Bit Timer in Each ePWM

Module

· On-Chip Memory

– Flash, SARAM, OTP, Boot ROM Available

· 128-Bit Security Key/Lock

– Protects Secure Memory Blocks

– Prevents Firmware Reverse Engineering

· Serial Port Peripherals

– One SCI (UART) Module

– One SPI Module

– One Inter-Integrated-Circuit (I2C) Bus

· Advanced Emulation Features

– Analysis and Breakpoint Functions

 

– Real-Time Debug via Hardware

· 2802x, 2802xx Packages

– 38-Pin DA Thin Shrink Small-Outline Package (TSSOP)

– 48-Pin PT Low-Profile Quad Flatpack (LQFP)