Archive for June, 2014
Break Microcontroller PIC16F628A Content
We can break Microcontroller PIC16F628A Content, please view the Microcontroller PIC16F628A features for your reference:
GENERAL DESCRIPTION
The PIC16F627A/628A/648A are 18-Pin FLASH-based members of the versatile PIC16CXX family low cost, high performance, CMOS, fully-static, 8-bit microcontroller.
All PICmicro® microcontrollers employ an advanced RISC architecture. The PIC16F627A/628A/648A have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data.
The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available, complemented by a large register set.
PIC16F628A microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. PIC16F627A/628A/648A devices have integrated features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption.
The PIC16F628A has 8 oscillator configurations. The single-pin RC oscillator provides a low cost solution. The LP oscillator minimizes power consumption, XT is a standard crystal, and INTOSC is a self-contained precision two-speed internal oscillator to read MCU. The family HS is for High-Speed crystals. The EC mode is for an external clock source.
Break MCU PIC16F631 Flash
We can Break MCU PIC16F685 flash, please view the MCU PIC16F685 features for your reference:
High-Performance RISC CPU:
· Only 35 instructions to learn:
– All single-cycle instructions except branches
· Operating speed:
– DC – 20 MHz oscillator/clock input
– DC – 200 ns instruction cycle
· Interrupt capability
· 8-level deep hardware stack
· Direct, Indirect and Relative Addressing modes
Special Microcontroller Features:
· Precision Internal Oscillator:
– Factory calibrated to ± 1%
– Software selectable frequency range of 8 MHz to 32 kHz
– Software tunable
– Two-Speed Start-up mode
– Crystal fail detect for critical applications
– Clock mode switching during operation for power savings
· Power-Saving Sleep mode
· Wide operating voltage range (2.0V-5.5V)
· Industrial and Extended Temperature range
· Power-on Reset (POR)
· Power-up Timer (PWRTE) and Oscillator Start-up Timer (OST)
· Brown-out Reset (BOR) with software control option and for MCU reading
· Enhanced low-current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable
· Multiplexed Master Clear/Input pin
· Programmable code protection
· High Endurance Flash/EEPROM cell:
– 100,000 write Flash endurance
– 1,000,000 write EEPROM endurance
– Flash/Data EEPROM retention: > 40 years
· Enhanced USART module:
– Supports RS-485, RS-232 and LIN 2.0
– Auto-Baud Detect
– Auto-wake-up on Start bit
Break IC PIC16F685 Code
We can Break IC PIC16F685 Code, please view the Ic PIC16F685 features for your reference:
The PIC16F685 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) is physically implemented for the PIC16F631, the first 2K x 14 (0000h-07FFh) for the PIC16F677/PIC16F687, and the first 4K x 14 (0000h-0FFFh) for the PIC16F685/PIC16F689/ PIC16F690 when Break Ic. Accessing a location above these boundaries will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h.
The data memory (see Figures 2-6 through 2-8) is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The CALL, RETURN RETFIE, RETLW.
General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank. Register locations F0h-FFh in Bank 1, 170h-17Fh in Bank 2 and 1F0h-1FFh in Bank 3 point to addresses 70h-7Fh in Bank 0. The actual number of General Purpose Resisters (GPR) in each Bank depends on the device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when Reset Vector 0000h read. RP<1:0> of the STATUS register are the bank select bits:
The register file is organized as 128 x 8 in the PIC16F687 and 256 x 8 in the PIC16F685/PIC16F689/PIC16F690. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”) by Break IC PIC16F685 Code.
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device for MCU Reading (see Tables 2-1 through 2-4). These registers are static RAM.
The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Registers related to the operation of peripheral features are described in the section of that peripheral feature.
Recover Chip PIC16F689 Flash
We can Recover Chip PIC16F689 Flash, please view the CHIP PIC16F689 features below for your reference:
High-Performance RISC CPU:
· Only 35 Instructions to Learn:
– All single-cycle instructions except branches
· Operating Speed:
– DC – 20 MHz oscillator/clock input
– DC – 200 ns instruction cycle
· Interrupt Capability
· 8-level Deep Hardware Stack
Low-Power Features:
· Standby Current:
– 50 nA @ 2.0V, typical
· Operating Current:
– 11 ìA @ 32 kHz, 2.0V, typical
– 220 ìA @ 4 MHz, 2.0V, typical
· Watchdog Timer Current:
– 1 ìA @ 2.0V, typical
· Direct, Indirect and Relative Addressing modes
Peripheral Features:
Special Microcontroller Features:
· Precision Internal Oscillator:
– Factory calibrated to ±1%
– Software selectable frequency range of 8 MHz to 125 kHz
– Software tunable
– Two-Speed Start-Up mode
– Crystal fail detect for critical applications
– Clock mode switching during operation for power savings
· Power-Saving Sleep mode
· Wide Operating Voltage Range (2.0V-5.5V)
· Industrial and Extended Temperature Range
· Power-on Reset (POR)
· Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
· Brown-out Reset (BOR) with Software Control Option
· Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable
· Multiplexed Master Clear with Weak Pull-up or Input Only Pin
· Programmable Code Protection
· High-Endurance Flash/EEPROM Cell:
– 100,000 write Flash endurance
– 1,000,000 write EEPROM endurance
– Flash/Data EEPROM retention: > 40 years
· 12 I/O Pins with Individual Direction Control:
– High-current source/sink for direct LED drive
– Interrupt-on-change pin
– Individually programmable weak pull-ups
– Ultra Low-Power Wake-up
· Analog Comparator module with:
– Two analog comparators
– Programmable On-chip Voltage Reference (CVREF) module (% of VDD)
– Comparator inputs and outputs externally accessible
· A/D Converter:
– 10-bit resolution and 8 channels
· Timer0: 8-bit Timer/Counter with 8-bit Programmable Prescaler
· Enhanced Timer1:
– 16-bit timer/counter with prescaler
– External Timer1 Gate (count enable)
– Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected
· Enhanced USART Module:
– Supports RS-485, RS-232, LIN 2.0/2.1 and J2602
– Auto-Baud Detect
– Auto-wake-up on Start bit
· In-Circuit Serial Programming™ (ICSP™) via two pins
Copy Chip PIC16F73 Program
We can Copy Chip PIC16F73 Program, please view the Chip PIC16F73 features for your reference:
The PIC16C7X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit chips with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family. All PIC16/17 chips employ an advanced RISC architecture. The PIC16CXX chip family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.
PIC16CXX chips typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit chips in their class. The PIC16C72 has 128 bytes of RAM and 22 I/O pins.
In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module and one serial port. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. Also a 5-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.
The PIC16C73/73A devices have 192 bytes of RAM, while the PIC16C76 has 368 byes of RAM. Each device has 22 I/O pins. In addition, several peripheral features are available including: three timer/counters, two Capsuited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.
The PIC16C7X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption which can be used for MCU Cracking.
There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets.
A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock up.
A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-Time-Programmable (OTP) version is suitable for production in any volume.
The PIC16C7X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this chip series perfect for all applications with space limitations.
Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C7X very versatile even in areas where no chip use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor applications).
Copy MCU XC18V04PC44C Program
We can Copy MCU XC18V04PC44C Program, please view below MCU XC18V04PC44C features for your reference:
XC18V00 Series In-System-Programmable Configuration PROMs:
Product Specification:
In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
♦ Endurance of 20,000 Program/Erase Cycles
♦ Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA Configuration
Simple Interface to the FPGA
Cascadable for Storing Longer or Multiple Bitstreams
Low-Power Advanced CMOS FLASH Process Dual Configuration Modes
♦ Serial Slow/Fast Configuration (up to 33 MHz)
♦ Parallel (up to 264 Mb/s at 33 MHz)
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
Design Support Using the Xilinx ISE™ Foundation™ Software Packages
Available in PC20, SO20, PC44, and VQ44 Packages
Lead-Free (Pb-Free) Packaging
Description
Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-to- use, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.
After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.
Copy IC DSP TMS320LF2401AVFA Flash
We can Copy IC DSP TMS320LF2401AVFA Flash, please view below IC DSP TMS320LF2401AVFA features for your reference:
High-Performance Static CMOS Technology
− 25-ns Instruction Cycle Time (40 MHz)
− 40-MIPS Performance
− Low-Power 3.3-V Design Based on TMS320C2xx DSP CPU Core
− Code-Compatible With F243/F241/C242
− Instruction Set and Module Compatible With F240 Flash (LF) and ROM (LC) Device Options
− LF240xA: LF2407A, LF2406A, LF2403A, LF2402A
− LC240xA: LC2406A, LC2404A, LC2403A, LC2402A
On-Chip Memory
− Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors) or ROM
− Programmable “Code-Security” Feature for the On-Chip Flash/ROM
− Up to 2.5K Words x 16 Bits of Data/Program RAM
− 544 Words of Dual-Access RAM
− Up to 2K Words of Single-Access RAM Boot ROM (LF240xA Devices)
− SCI/SPI Bootloader Up to Two Event-Manager (EV) Modules (EVA and EVB), Each Includes:
− Two 16-Bit General-Purpose Timers
− Eight 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable:
− Three-Phase Inverter Control
− Center- or Edge-Alignment of PWM Channels
− Emergency PWM Channel Shutdown With External PDPINTx Pin
− Programmable Deadband (Deadtime) Prevents Shoot-Through Faults
− Three Capture Units for Time-Stamping of External Events
− Input Qualifier for Select Pins
− On-Chip Position Encoder Interface Circuitry to faciliate the process of IC Cloning
− Synchronized A-to-D Conversion
− Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control
− Applicable for Multiple Motor and/or Converter Control
External Memory Interface (LF2407A)
− 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O Watchdog (WD) Timer Module 10-Bit Analog-to-Digital Converter (ADC)
− 8 or 16 Multiplexed Input Channels
− 500-ns MIN Conversion Time
− Selectable Twin 8-State Sequencers Triggered by Two Event Managers Controller Area Network (CAN) 2.0B Module (LF2407A, 2406A, 2403A)
Serial Communications Interface (SCI)
16-Bit Serial Peripheral Interface (SPI)
(LF2407A, 2406A, LC2404A, 2403A)
Phase-Locked-Loop (PLL)-Based Clock
Generation
Up to 40 Individually Programmable,
Multiplexed General-Purpose Input / Output (GPIO) Pins
Up to Five External Interrupts (Power Drive
Protection, Reset, Two Maskable Interrupts) Power Management:
− Three Power-Down Modes
− Ability to Power Down Each Peripheral Independently
Real-Time JTAG-Compliant Scan-Based
Emulation, IEEE Standard 1149.1† (JTAG)
Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler, Assembler/ Linker, and Code Composer Studio Debugger
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control Support Package Options
− 100-Pin LQFP PZ (2406A, LC2404A)
− 64-Pin TQFP PAG (LF2403A, LC2403A, LC2402A)
− 64-Pin QFP PG (2402A)
Extended Temperature Options (A and S)
− A: − 40°C to 85°C
− S: − 40°C to 125°C
Attack Chip DSP TMS320LF2406APZAR Flash
We can Attack Chip DSP TMS320LF2406APZAR Flash, below is the Chip DSP TMS320LF2406APZAR features for your reference:
High-Performance Static CMOS Technology
− 25-ns Instruction Cycle Time (40 MHz)
− 40-MIPS Performance
− Low-Power 3.3-V Design
D Based on TMS320C2xx DSP CPU Core
− Code-Compatible With F243/F241/C242
− Instruction Set and Module Compatible With F240 D Flash (LF) and ROM (LC) Device Options
− LF240xA: LF2407A, LF2406A, LF2403A, LF2402A
− LC240xA: LC2406A, LC2404A, LC2403A, LC2402A D On-Chip Memory
− Up to 32K Words x 16 Bits of Flash EEPROM (4 Sectors) or ROM
− Programmable “Code-Security” Feature for the On-Chip Flash/ROM
− Up to 2.5K Words x 16 Bits of Data/Program RAM
− 544 Words of Dual-Access RAM
− Up to 2K Words of Single-Access RAM D Boot ROM (LF240xA Devices)
− SCI/SPI Bootloader D Up to Two Event-Manager (EV) Modules (EVA and EVB), Each Includes:
− Two 16-Bit General-Purpose Timers
− Eight 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable:
− Three-Phase Inverter Control can be used for MCU Cracking
− Center- or Edge-Alignment of PWM Channels
− Emergency PWM Channel Shutdown With External PDPINTx Pin
− Programmable Deadband (Deadtime) Prevents Shoot-Through Faults
− Three Capture Units for Time-Stamping of External Events
− Input Qualifier for Select Pins
− On-Chip Position Encoder Interface Circuitry
− Synchronized A-to-D Conversion
− Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor
Control
− Applicable for Multiple Motor and/or Converter Control
D External Memory Interface (LF2407A)
− 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
D Watchdog (WD) Timer Module
D 10-Bit Analog-to-Digital Converter (ADC)
− 8 or 16 Multiplexed Input Channels
− 500-ns MIN Conversion Time
− Selectable Twin 8-State Sequencers
Triggered by Two Event Managers
D Controller Area Network (CAN) 2.0B Module
(LF2407A, 2406A, 2403A)
D Serial Communications Interface (SCI)
D 16-Bit Serial Peripheral Interface (SPI) (LF2407A, 2406A, LC2404A, 2403A)
D Phase-Locked-Loop (PLL)-Based Clock
Generation
D Up to 40 Individually Programmable, Multiplexed General-Purpose Input / Output (GPIO) Pins
D Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts)
D Power Management:
− Three Power-Down Modes
− Ability to Power Down Each Peripheral Independently
D Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1† (JTAG)
D Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler, Assembler/ Linker, and Code Composer Studio Debugger
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control Support
D Package Options
− 144-Pin LQFP PGE (LF2407A)
− 100-Pin LQFP PZ (2406A, LC2404A)
− 64-Pin TQFP PAG (LF2403A, LC2403A, LC2402A)
− 64-Pin QFP PG (2402A) D Extended Temperature Options (A and S)
− A: − 40°C to 85°C
− S: − 40°C to 125°C
Attack Microcontroller TMS320C32PCM40 Firmware
We can Attack Microcontroller TMS320C32PCM40 Firmware, please view below Microcontroller TMS320C32PCM40 features for your reference:
High-Performance Floating-Point DSP
– TMS320C32-60 (5 V)
33-ns Instruction Cycle Time
330 Million Operations Per Second (MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS), 30 Million Instructions Per Second (MIPS)
– TMS320C32-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
– TMS320C32-40 (5 V)
50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
32-Bit High-Performance CPU
16- / 32-Bit Integer and 32- / 40-Bit
Floating-Point Operations
32-Bit Instruction Word, 24-Bit Addresses
Two 256 × 32-Bit Single-Cycle, Dual-Access
On-Chip RAM Blocks
Flexible Boot-Program Loader to Unlocking Microcontroller
On-Chip Memory-Mapped Peripherals:
– One Serial Port
– Two 32-Bit Timers
– Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
Enhanced External Memory Interface That Supports 8- / 16- / 32-Bit-Wide External RAM for Data Access and Program Execution From 16- / 32-Bit-Wide External RAM
TMS320C30 and TMS320C31 Object Code Compatible Fabricated using 0.7 µm Enhanced Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI) 144-Pin Plastic Quad Flat Package ( PCM Suffix ) 5 V Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits
Two Sets of Memory Strobes (STRB0 and STRB1) and One I / O Strobe (IOSTRB)
Allow Zero-Glue Logic Interface to Two
Banks of Memory and One Bank of External
Peripherals
Separate Bus-Control Registers for Each
Strobe-Control Wait-State Generation,
External Memory Width, and Data Type Size
STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes)
Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes
Attack MCU TMS320F241PG Heximal
We can Attack MCU TMS320F241PG Heximal, please view the MCU TMS320F241PG features below for your reference:
High-Performance Static CMOS Technology
D Includes the T320C2xx Core CPU
– Object-Compatible With the TMS320C2xx
– Source-Code-Compatible With TMS320C25
D Single 10-Bit Analog-to-Digital Converter
(ADC) Module With 8 Multiplexed Input Channels
D 26 Individually Programmable, Multiplexed
General-Purpose I / O (GPIO) Pins
– Upwardly Compatible With TMS320C5x
– 50-ns Instruction Cycle Time
Pin Compatible to Emulation Device
TMS320F241 (64-Pin/68-Pin)
Code Compatible to Emulation Devices TMS320F243 and TMS320F241
Commercial and Industrial Temperature Available
Memory
– 544 Words x 16 Bits of On-Chip Data/Program Dual-Access RAM (DARAM)
– 4K Words x 16 Bits of On-chip Program ROM Event-Manager Module
– Eight Compare/ Pulse-Width Modulation (PWM) Channels
– Two 16-Bit General-Purpose Timers With Six Modes, Including Continuous Up and Up / Down Counting
– Three 16-Bit Full Compare Units With Phase-Locked-Loop (PLL)-Based Clock Watchdog (WD) Timer Module
Serial Communications Interface (SCI) in order to Clone IC
Five External Interrupts (Power Drive Protection, Reset, NMI, and Two Maskable Interrupts)
Three Power-Down Modes for Low-Power
Operation
Scan-Based Emulation
Development Tools Available:
– Texas Instruments (TI) ANSI Compiler, Assembler / Linker, and
C-Source Debugger
– Full Range of Emulation Products
– Self-Emulation (XDS510)
– Third-Party Digital Motor Control and Fuzzy-Logic Development Support
68-Pin PLCC FN Package
64-Pin QFP PG Package
Deadband
– Three Capture Units (Two With Quadrature Encoder-Pulse Interface Capability)
TMS320C2xx generation of 16-bit fixed-point DSPs.
The TMS320F241 device is fully compatible with the C242 to allow emulation during prototype development. (These two devices share similar core and peripherals.) This new family is optimized for digital motor / motion control applications
The DSP controllers combine the enhanced TMS320 architectural design of the ’C2xx core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications
These peripherals include the event manager module, which provides general-purpose timers and PWM registers to generate PWM outputs, and a single,10-bit analog-to-digital converter (ADC), which can perform conversion within 1 µs.