Archive for June, 2013

PostHeaderIcon Extract Chip PIC16C57A Program

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The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration when Extract Chip program.

Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator if Extract Chip program.

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed before Extract Chip program.

The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> after Extract Chip program.

Bit 5 of the STATUS register provides page information to bit 9 of the PC For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word when Extract Chip program.

However, PC<8> does not come from the instruction word, but is always cleared. The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction if Extract Chip program.

After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected before Extract Chip program.

Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered after Extract Chip program.

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In practice the maximum resolution which can be achieved with a standard 100× objective (NA = 0.9) is about 0.3 µm. In order to obtain higher working NA the refractive index of the medium between the objective and the specimen must be increased. There are objectives that allow imaging in water (n = 1.33) and immersion oil (n = 1.51). That increases the maximum resolution up to 0.2 µm for 100× objective. Another way of increasing the resolution is using a shorter wavelength. By shifting to near-ultraviolet (NUV) light with 360 nm wavelength, the  resolution can be increased to 0.18 µm, but this requires special CCD cameras.

Some microscopes have additional features aimed at increasing the contrast of the image and thereby achieving the highest possible resolution. These are darkfield (DF) illumination, differential interference contrast [114], phase contrast [115] and confocal imaging [116]. All the major microscope manufacturers such as Nikon, Olympus, Carl Zeiss and Leica offer a wide range of models from basic to high-end; the latter have all the features necessary to achieve the highest resolution. There are models specifically designed for semiconductor analysis such as the Nikon Optiphot 200C [117], Olympus MX50 [118], Zeiss Axiotron 2 [119] and Leica INM100 [120].

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Normally a microscope objective has at least two parameters printed on it – magnification and numerical aperture (NA). Modern optical microscopes provide magnification up to 9,000× and 500× magnification is provided by most modern microscopes. Numerical aperture determines the resolving power of an objective, but the total resolution of a microscope system is also dependent upon the numerical aperture of projection optics. The higher the numerical aperture of the total system the better the resolution. The numerical aperture is related to the angle µ which is one-half of the angular aperture at which the light cone comes to the specimen surface: NA = n sin(µ). The relationship between the numerical aperture and the resolution can used for observation.

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Optical imaging for layout reconstruction

The most important tool for reverse engineering silicon chips down to 0.18 µm feature size is an optical microscope with a CCD camera to produce mosaics of high-resolution photographs of the chip surface. Not every microscope would do. As light cannot pass through the chip, the microscope should have reflected light illumination. The image should be sharp and without geometric distortion and colour aberration, otherwise it will not be possible to stick all the images together. The most important parameters of the microscope are resolution and magnification. The resolution of a microscope mainly depends upon its objective lenses and is defined as the smallest distance between two points on a specimen that can still be distinguished as two separate entities. Resolution is a somewhat subjective value in microscopy because at high magnification an image may appear non-sharp but still be resolved to the maximum ability of the objective.

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A slightly different approach is required for reverse engineering CPLDs and FPGAs. Even if the security protection is defeated and the attacker manages to extract the configuration bitstream file from the device, he will have to spend a substantial amount of time and effort to convert it into the logic equations and primitive blocks for further simulation and analysis. Meantime, there are some companies on the market, for example Bottom Line Technologies [111], which provide bitstream reverse engineering for CPLDs and FPGAs.

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When it comes to reverse engineering smartcards and microcontrollers, both structural and program-code reverse engineering are required to understand how the device works. First, the security protection needs to be understood by partial reverse engineering of the chip area associated with it. Thus if memory bus encryption was used, the hardware responsible for this should be reverse engineered. Then, finally, the internal memory contents have to be extracted and disassembled to understand device functions.

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Reverse engineering is a technique aimed at understanding the structure of a semiconductor device and its functions. In case of an ASIC or a custom IC, that means extracting information about the location of all the transistors and interconnections. In order to succeed, a general knowledge of IC and VLSI design is required. All the layers formed during chip fabrication are removed one-by-one in reverse order and photographed to determine the internal structure of the chip. In the end, by processing all the acquired information, a standard netlist file can be created and used to simulate the device. This is a tedious and time-consuming process, but there are some companies, for example Chipworks [110], which do such work as a standard service.

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For wet chemical etching we used the Nitrox wet etchant – one of the most effective etching agents for silicon nitride and silicon dioxide passivation layers which selectively removes the passivation layers of integrated circuits while preserving full device functionality.

To observe deeper layers, top aluminium layers were etched away with a 20% water solution of hydrochloric acid HCl or 33% water solution of potassium hydroxide KOH. Although wet etching does not provide good uniformity across the die surface, a lot of information about the internal chip structure can be obtained. Examples of such operations are presented

As can be seen, wet chemical etching does not provide very good uniformity over the surface resulting in some areas where the top metal is not entirely removed and other areas where the underneath layer is starting to be etched. Also, as can be seen in Figure 57, some long metal wires lifted off the surface obstructing the view.

Deprocessing using wet chemical etching does not require much more experience than decapsulation and all the necessary chemicals can be bought for about £100. Care must be taken during the work, as these chemicals are very aggressive and dangerous, especially the ones containing fluorine.

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For wet and dry etching, each type of material requires certain etchants to be used. Some of them have very high selectivity and remove only the desired layer; others affect many layers at a time. For example, silicon and polysilicon can be etched with a mixture of hydrofluoric acid HF and nitric acid HNO3, but HF etches silicon oxide as well.

Other etchants are used for specific purposes, such as doping etchants with a doping-dependent etch rate to make visible doping fronts and p-n junctions. Such etchants are used, for example, to make visible the contents of VTROM in modern smartcards [8]. More information about different etchants and etching technology can be found in the literature on failure analysis techniques.

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The removal of material is strongly anisotropic (directional). Only the surfaces hit by the ions are removed, sides perpendicular to their paths are not touched. Mechanical polishing is performed with the use of abrasive materials. The process is time-consuming and requires special machines to maintain the planarity of the surface. From the inspection perspective, the advantages of using polishing over wet and dry etching techniques is the ability to remove layer by layer and view features in the area of interest within the same plane. It is especially useful on multilayer interconnect processes fabricated with advanced planarisation techniques.