Archive for August, 2012

PostHeaderIcon Break secured IC PIC16F716 Firmware

We can Break secured IC PIC16F716 Firmware, please view the IC PIC16F716 features for your reference:

The PIC16F7X devices have a 13-bit program counter capable of addressing an 8K word x 14-bit program memory space. The PIC16F77/76 devices have 8K words of FLASH program memory and the PIC16F73/74 devices have 4K words when Break secured IC.

The program memory maps for PIC16F7X devices are shown in Figure 2-1. Accessing a location above the physically implemented address will cause a wrap around Firmware.

The RESET Vector is at 0000h and the Interrupt Vector is at 0004h. The Data Memory is partitioned into multiple banks, which contain the General Purpose Registers and the Special Function Registers from secured IC Firmware.

Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits: Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers after Secured IC Breaking.

Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers when Break secured IC Firmware.

Some frequently used Special Function Registers from one bank may be mirrored in another bank for firmware reduction and quicker access. The register file (shown in Figure 2-2 and Figure 2-3) can be accessed either directly, or indirectly, through the File Select Register FSR Firmware.

The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM after IC breaking.

The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section when Break secured IC Firmware. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.

PostHeaderIcon Reverse Microchip MCU PIC16LF77 Flash

We can Reverse Microchip mcu PIC16LF77 Flash, please view the Microchip mcu PIC16LF77 features for your reference:

Low power, high speed CMOS FLASH technology

Fully static design

Wide operating voltage range: 2.0V to 5.5V

High Sink/Source Current: 25 mA

Industrial temperature range when Reverse Microchip mcu flash

Low power consumption:

– < 2 mA typical @ 5V, 4 MHz

– 20 µA typical @ 3V, 32 kHz

– < 1 µA typical standby current if Reverse Microchip mcu

PIC16F73/76 devices are available only in 28-pin packages, while PIC16F77 devices are available in 40-pin and 44-pin packages.

All devices in the PIC16F7X family share common architecture, with the following differences from mcu recovery:

The PIC16F73 and PIC16F76 have one-half of the total on-chip memory of the PIC16LF77

The 28-pin devices have 3 I/O ports, while the 40/44-pin devices have 5

The 28-pin devices have 11 interrupts, while the 40/44-pin devices have 12 after Reverse Microchip mcu

The 28-pin devices have 5 A/D input channels, while the 40/44-pin devices have 8

The Parallel Slave Port is implemented only on the 40/44-pin devices before Microchip mcu flash reverse engineering

Additional information may be found in the PICmicro™ Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website if Reverse Microchip mcu.

The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules of Microchip mcu flash memory.

PostHeaderIcon MCU Code Restoration

Another big problem for EPROM, EEPROM and Flash memories that affects the hardware security of the MCU devices is data remanence. Many MCUs with these types of memory have a security fuse which, once activated, cannot be reset until the whole memory content is first erased. Manufacturers put a lot of effort into hardware design to ensure that the security fuse will not be deactivated by manipulation of external signals such as power glitches. They made very good progress, and very few of the modern MCUs can be broken using tricks such as applying power glitches during the chip erase operation to terminate the memory erase without affecting the erase of the security fuse, or exposing the chip to UV light for long enough to erase the security fuse but not long enough to destroy the memory source code contents.

But recent revisions of MCUs are not sensitive to such restoration. In modern chips, an additional voltage monitoring circuit is usually implemented, causing a reset of the hardware programming interface or preventing any write/erase operations below or above certain voltages. What was wrongly assumed is that information must disappear from the memory after it was erased. In fact some traces of the data are still left after the erase operation, and to get the information back we just have to find the right method to measure the residual charge on a floating gate, or a threshold of a memory transistor. This is not an easy task, but if the security fuse was deactivated during the chip erase operation, the memory can be accessed normally. That allows the MCU code restoration engineer to measure the response from each transistor inside the array by sequential reading of each memory location and microprobing the internal memory bus. Of course it is not a trivial task, but a determined and experienced mcu code restoration can do this. In some MCUs the threshold level of each transistor can be measured in fully non-invasive mcu code restoration way by playing with the interface and power supply voltages. This is possible because very often the memory sense circuit uses the power supply voltage as a reference.

PostHeaderIcon EPROM advantage when MCU Code Decryption

In terms of non-invasive MCU Code Decryption, EPROM memory has some advantages over EEPROM and Flash memories as it is more robust against power glitch decryptions. This happens because it has a simpler structure, larger cell size, thicker gate oxide and no on-chip high-voltage charge pumps.

The sense amplifiers used to distinguish between ‘0’ and ‘1’ logic states are much simpler in EPROM and less sensitive to the power supply voltage. Against semi-invasive mcu code decryption, EPROM memory is also better than EEPROM and Flash. For example, the fault injection decryption that will be discussed later can be used to modify the contents of the cell but for EPROM much higher power is required. That makes OTP microcontrollers more attractive in the applications where high security is required. Unfortunately modern microcontrollers do not use this type of memory any more as it cannot be reprogrammed, has lower density than the Flash memory and is thus more expensive. That forces semiconductor manufacturers to introduce additional protection against unauthorised access to the memory contents. For example, modern smartcards do not have hardware control for access to the on-chip Flash and EERPOM memories, but only a bootstrap loader located in the Flash memory that overwrites itself during first initialisation, eliminating any possible access to the information (unless implemented by the customer). Hardware access to the memory has multi-level security protection ensuring that access will not be granted unless all the requirements are met. In some microcontrollers, very sophisticated access password protection is implemented.

PostHeaderIcon Recovery Microcontroller PIC16LF76 Firmware

We can Recovery microcontroller PIC16LF76 Firmware, please view the microcontroller PIC16LF76 features for your reference:

PIC16LF76 devices are available only in 28-pin packages, while PIC16LF76 devices are available in 40-pin and 44-pin packages. All devices in the PIC16F7X family share common architecture, with the following differences when Recovery:

The PIC16LF76 have one-half of the total on-chip memory of the PIC16LF76

The 28-pin devices have 3 I/O ports, while the 40/44-pin devices have 5 if microcontroller Firmware recovery.

The 28-pin devices have 11 interrupts, while the 40/44-pin devices have 12

The 28-pin devices have 5 A/D input channels, while the 40/44-pin devices have 8.

The Parallel Slave Port is implemented only on the 40/44-pin devices’ Microcontroller firmware

The available features are summarized in Table 1-1.

Block diagrams of the PIC16LF76 after Recovery.

Additional information may be found in the PICmicro™

Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website when Recovery microcontroller.

The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended recoverying for a better understanding of the device architecture and operation of the peripheral modules Microcontroller Firmware.

There are two memory blocks in each of these PICmicro® MICROCONTROLLERs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section before Recovery Microcontroller Firmware.

The Program Memory can be recovery internally by user code (see Section 3.0). Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual (DS33023) after Recovery MCU.

PostHeaderIcon MCU code reverse engineering Roadmap

Technological progress on its own is increasing the costs to MCU code reverse engineering. Ten years ago it was possible to use a laser cutter and a simple probing station to get access to any point on the chip surface, but for modern deep submicron semiconductor chips very sophisticated and expensive technologies must be used. That excludes most potential MCU code reverse engineering. For example, the structure of the Microchip PIC16F877 microcontroller can be easily observed and reverse engineered under a microscope. The second metal layer and polysilicon layer can still be seen even if buried under the top metal layer. This is possible because each subsequent layer in the fabrication process follows the shape of the previous layer. Under a microscope the observer sees not only the highest layer but also edges that reveal the structure of the deeper layers. In 0.5 µm and smaller technologies, for example in the Microchip PIC16F877A microcontroller, each predecessor layer is planarised using chemical-mechanical planarisation (CMP) process before applying the next layer. As a result the top metal layer does not show the impact of the deeper layers. The only way to reveal the structure of the deeper layers is by removing the top metal layers either mechanically or chemically.

As can be seen from all the shown examples, hardware security in microcontrollers and smartcards is being constantly improved. Because the tools for mcu code reverse engineering are becoming more sophisticated, better and better security protection is required. Rapid co-evolution is driven by this continuous battle between mcu manufacturers and mcu code reverse engineer.

Another threat that must be considered is that a great deal of second-hand semiconductor manufacturing and testing equipment appears on the market. It cannot be used to reverse engineering high-end products, but should be enough to reverse engineering MCUs manufactured with older technology. For example, while 90 nm manufacturing technology is currently leading-edge, most microcontrollers are produced with 0.35 µm technology and smartcards with 0.25 µm technology.

PostHeaderIcon Break IC PIC16LF74 Memory

We can Break IC PIC16LF74 Memory, please view the IC PIC16LF74 features for your reference:

High performance RISC CPU

Only 35 single word instructions to learn

All single cycle instructions except for program branches which are two-cycle

Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle when Break IC

Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM)

Pinout compatible to the PIC16LF74

Pinout compatible to the PIC16LF74 if Break IC

Interrupt capability (up to 12 sources)

Eight level deep hardware stack

Direct, Indirect and Relative Addressing modes

 

Brown-out detection circuitry for

Parallel Slave Port (PSP), 8-bits wide with if Break IC

Universal Synchronous Asynchronous Receiver

8-bit, up to 8-channel Analog-to-Digital converter

Synchronous Serial Port (SSP) with SPI (Master

Timer2: 8-bit timer/counter with 8-bit period when Break IC

Timer0: 8-bit timer/counter with 8-bit prescaler

Timer1: 16-bit timer/counter with prescaler,

Programmable memory protection

Power saving SLEEP mode

Selectable oscillator options before Break IC

In-Circuit Serial Programming (ICSP) via two

Watchdog Timer (WDT) with its own on-chip RC

Power-on Reset (POR) after Break IC

Power-up Timer (PWRT) and Processor read access to program memory Oscillator Start-up Timer (OST) oscillator for reliable operation pins can be incremented during SLEEP via external crystal/clock register, prescaler and postscaler

Two Capture, Compare, PWM modules

– Capture is 16-bit, max. resolution is 12.5 ns

– Compare is 16-bit, max. resolution is 200 ns when Break IC

– PWM max. resolution is 10-bit mode) and I2C (Slave) Transmitter (USART/SCI) external RD, WR and CS controls (40/44-pin only) Brown-out Reset (BOR) if Break IC

Low power, high speed CMOS FLASH technology

Fully static design

Wide operating voltage range: 2.0V to 5.5V

High Sink/Source Current: 25 mA

Industrial temperature range after Break IC

Low power consumption:

– < 2 mA typical @ 5V, 4 MHz

– 20 µA typical @ 3V, 32 kHz

– < 1 µA typical standby current

PostHeaderIcon Reverse Microchip MCU PIC16F77 Flash

We can Reverse Microchip mcu PIC16F77 Flash, please view the Microchip mcu PIC16F77 features for your reference:

  • High performance RISC CPU
  • Only 35 single word instructions to learn
  • All single cycle instructions except for program branches which are two-cycle
  • Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle when Reverse Microchip mcu flash
  • Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM)
  • Pinout compatible to the PIC16C73B/74B/76/77
  • Pinout compatible to the PIC16F873/874/876/877
  • Interrupt capability (up to 12 sources) if Reverse Microchip mcu flash
  • Eight level deep hardware stack
  • Direct, Indirect and Relative Addressing modes
    • Brown-out detection circuitry for
      • Parallel Slave Port (PSP), 8-bits wide with
        • Universal Synchronous Asynchronous Receiver before Reverse Microchip mcu flash
          • 8-bit, up to 8-channel Analog-to-Digital converter
          • Synchronous Serial Port (SSP) with SPI (Master
            • Timer2: 8-bit timer/counter with 8-bit period after Reverse Microchip mcu flash
              • Timer0: 8-bit timer/counter with 8-bit prescaler
              • Timer1: 16-bit timer/counter with prescaler,
                • Programmable code protection
                • Power saving SLEEP mode
                • Selectable oscillator options when Reverse Microchip mcu flash
                • In-Circuit Serial Programming (ICSP) via two
                • Power-on Reset (POR)
                • Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST) oscillator for reliable operation pins can be incremented during SLEEP via external crystal/clock register, prescaler and postscaler after Reverse Microchip mcu flash.

  • Two Capture, Compare, PWM modules

– Capture is 16-bit, max. resolution is 12.5 ns

– Compare is 16-bit, max. resolution is 200 ns when Reverse Microchip mcu flash

– PWM max. resolution is 10-bit mode) and I2C (Slave) Transmitter (USART/SCI) external RD, WR and CS controls (40/44-pin only) Brown-out Reset (BOR) if Break IC.

 

PostHeaderIcon IC Code Break’s intermediate approach

More often an intermediate approach is used when the IC is built from separate blocks but each block uses glue logic design as in, for example, the Cypress CY7C63001A microcontroller. In this case an ic code breaker could more easily trace the bus and control lines between the blocks, and launch invasive or semi-invasive ic code break on the chip. Glue logic design does not eliminate the possibility of non-invasive ic code break, but as the performance increases, faster and more expensive equipment is required. Semi-invasive ic code breaks will also face problems due to disguised design blocks. Of course the breaker could automate the process by running an exhaustive search and trying to break all possible areas. Definitely this approach would take a long time and may in the end not be successful. On the other hand, an ic code break could be applied directly to the memory itself or its control circuit, because they cannot be implemented in the same glue logic structure and stay visibly separate.

PostHeaderIcon Crack IC Code’s other improvement

Other improvements in making invasive ic code crack more expensive involve using a top metal sensor mesh. All paths in this mesh are continuously monitored for interruptions and short circuits, and cause reset or zeroing of the EEPROM memory if alarmed. Normally such protection is not used in ordinary microcontrollers because, firstly, it increases the design cost and, secondly, it can be triggered unintentionally in abnormal working conditions such as high electromagnetic noise, low or high temperatures, irregular clock signal or power supply interruptions. Instead, ordinary microcontrollers adopt the less expensive approach of placing a fake top layer mesh, but this still remains a very effective annoyance for optical analysis and microprobing ic code crack. In smartcards such meshes are implemented properly with the sensor wires going between the power supply and ground wires. Some design flaws were found in such implementations making microprobing ic code cracks possible. Also such meshes do not protect against non-invasive ic code cracks, and some semi-invasive ic code cracks are still possible because the mesh has gaps between the wires and light can pass through it down to the active areas of the circuit.